Empirical DC compact model for source-gated transistors using TCAD simulation data

Patryk Golec; Radu A Sporea; Eva Bestelink; Benjamin Iniguez

doi:10.1109/LAEDC58183.2023.10209131

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Empirical DC compact model for source-gated transistors using TCAD simulation data

Patryk Golec, Radu A Sporea, Eva Bestelink and Benjamin Iniguez

Proceedings of the 2023 IEEE Latin American Electron Devices Conference (LAEDC)

2023 IEEE Latin American Electron Devices Conference (LAEDC) (Puebla, Mexico, 03/07/2023–05/07/2023)

12/2023

DOI: https://doi.org/10.1109/LAEDC58183.2023.10209131

Abstract

SGT

Compact modelling

Schottky barrier

A source-gated transistor (SGT) is a type of thin film transistor (TFT) with unique behaviors. Functionally, the SGT is designed to decrease the saturation voltage at a lower and often more stable saturation current in comparison to a standard TFT, which makes it preferable in some circuit applications. This is achieved by introducing additional effects especially around the source region which differentiate the SGT enough that it cannot be described by a standard TFT compact model. The work presented aims to create the first empirical SGT compact model which may be implemented in DC circuits. This compact model has been developed using the data obtained from an SGT TCAD model.

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Title: Empirical DC compact model for source-gated transistors using TCAD simulation data
Creators: Patryk Golec (Author) - University of Surrey, School of Computer Science and Electronic Engineering
Radu A Sporea (Author) - University of Surrey, School of Computer Science and Electronic Engineering
Eva Bestelink (Author) - University of Surrey, School of Computer Science and Electronic Engineering
Benjamin Iniguez (Author) - Universidad Rovira i Virgili
Publication Details: Proceedings of the 2023 IEEE Latin American Electron Devices Conference (LAEDC)
Conference: 2023 IEEE Latin American Electron Devices Conference (LAEDC) (Puebla, Mexico, 03/07/2023–05/07/2023)
Publisher: Institute of Electrical and Electronics Engineers (IEEE)
First online publication date: 11/08/2023
Publication Date: 12/2023
Date accepted for publication: 01/05/2023
Grants: EP/V002759/1, Engineering and Physical Sciences Research Council (United Kingdom, Swindon) - EPSRC
Identifiers: 99922864202346; WOS:001050975100029
Academic Unit: School of Computer Science and Electronic Engineering
Resource Type: Conference proceeding

Empirical DC compact model for source-gated transistors using TCAD simulation data

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