Abstract
We have recently demonstrated that, contrary to conventional TFT design rules, emissive pixels based on source‐gated transistor drivers benefit from choosing a source‐gate overlap of several microns. Using TCAD simulations we show that incorporating the SGT overlap capacitance with that of the conventional storage capacitor, pixel area can be optimized, with no adverse impact on data retention. For the technology considered, the optimum source‐gate overlap was 4 ‐ 8 μm, which is in the range of highest operating frequencies for source‐gated transistors.