Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Q Cui; M Si; Radu Sporea; X Guo

doi:10.1109/TED.2013.2251346

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Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Journal article

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Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

Q Cui, M Si, Radu Sporea and X Guo

IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.60(5), pp.1782-1785

01/05/2013

DOI: https://doi.org/10.1109/TED.2013.2251346

Abstract

Science & Technology

Technology

Physical Sciences

Engineering

Electrical & Electronic

Physics

Applied

Engineering

Physics

ENGINEERING

ELECTRICAL & ELECTRONIC

PHYSICS

APPLIED

Noise margin (NM)

thin-film transistor (TFT)

zero-V-GS load inverter

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Title: Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits
Creators: Q Cui
M Si
Radu Sporea
X Guo
Publication Details: IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol.60(5), pp.1782-1785
Publisher: IEEE-INST ELECTRICAL ELECTRONICS ENGINEERS INC
Date published: 01/05/2013
Date submitted: 09/07/2013
Identifiers: 99515898502346
Academic Unit: School of Computer Science and Electronic Engineering
Language: English
Resource Type: Journal article

Simple Noise Margin Model for Optimal Design of Unipolar Thin-Film Transistor Logic Circuits

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