Abstract
© 2015 IEEE.Software Defined Radio (SDR) is a key area to realise new software implementations for adaptive and reconfigurable communication systems without changing any hardware device or feature. A review on efficient use of limited bandwidth and increasing distributed satellite missions can lead to the need for a generic yet configurable communication platform that can handle multiple signals from multiple satellites with various modulation techniques, data rates and frequency bands that must be compatible to typical small satellite requirements. SDR is beneficial for space applications as it can provide the flexibility and re-configurability and this is driven by fast development times, new found heritage, reduced cost, and low mass Commercial Off-The-Shelf (COTS) components. The implementation of a combined System-On-Chip (SoC) and SDR communication platform enables additional reduction in cost as well as mass. This paper proposes a SDR architecture in which Field Programmable Gate Array (FPGA) System-on-Chip (SoC) is paired with a Radio Frequency (RF) programmable transceiver SoC to solve back-end and front-end re-configurability challenges respectively. The test-bed is aimed at implementing the signal processing software functions in both the dual-core ARM processors and associated FPGA fabric. The distribution of the functions between the FPGA fabric and dual-processor is based on profiling experiments using signal processing blocks, implemented on the development platform, in order to identify where bottlenecks exist. This paper discusses further the results from the new multi-signal / multi-satellite pipeline architecture and the subsequent bandwidth, data rate and processing requirements. Aspects of implementing and testing signal processing chains needed for CubeSat Telecommand, Telemetry and Control (TT&C) are presented together with initial results. Thus the proposed technology not only contributes for a lightweight and portable ground station but also for an on-board satellite transceiver.