Abstract
This paper presents a layout-driven analysis of a multi-branch CMOS current source derived from a Brokaw reference architecture. Although schematic-level simulations confirm correct current scaling and good matching between replicated branches, practical implementations are significantly affected by layout-induced parasitic effects. The proposed design generates multiple scaled output currents using replicated branches with cascode devices and active loads. A full-custom layout is implemented, followed by post-layout parasitic extraction and quantitative evaluation of the impact of interconnect capacitances on current accuracy. The results show that layout parasitics introduce measurable deviations in the replicated currents, even when symmetry and matching-oriented layout techniques are applied, highlighting the importance of layout-aware design methodologies for precision current sources.