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Simulation study of overlap capacitance in source-gated transistors for current-mode pixel drivers
Journal article   Open access  Peer reviewed

Simulation study of overlap capacitance in source-gated transistors for current-mode pixel drivers

Raymond Drury, Eva Bestelink and Radu A. Sporea
IEEE Electron Device Letters
02/07/2019

Abstract

TFT; OLED; Active matrix; Display; Schottky barrier; Pixel circuit; Energy efficiency; Layout optimization
Contrary to conventional design principles, currentdriven pixel drivers based on source-gated transistors (SGTs) achieve their optimal drive current and speed with a deliberate 5 -10μm gate-source overlap. Total pixel circuit area need not increase, as the additional device area can be compensated by reducing the pixel storage capacitor. Numerical simulations demonstrate the viability of SGTs for emissive pixel drivers and high gain, low power, robust circuits for emerging sensor arrays.
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https://doi.org/10.1109/LED.2019.2926351View
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