We present raised source/drain MOSFET devices with channel lengths down to 50 nm. The raised source/drain structures are fabricated by growing a selective epitaxial silicon layer in the source and drain regions of the MOSFET device after sidewall spacer creation and before HDD implant. The layers were grown in a low pressure LPCVD epitaxy reactor with a mixture of silane and dichlorosilane. A pre-epitaxy process that eliminates the need for a pre-epitaxy bake in hydrogen has been developed. In this study, we have varied the thickness of this selective epitaxial silicon layer to investigate the effect of this parameter on device performance. Reducing the channel length of the devices has a detrimental effect on SCE and DIBL. In this paper, we show how short channel performance can be retrieved by adding raised source/drain structures, and how increasing the thickness of these structures improves these parameters further.