The ultrathin channel nanocrystalline silicon transistor shows greatly improved switching performance and has demonstrated its candidacy for low power applications. In this work, by careful observation of the current-voltage and threshold voltage characteristics, we find that current percolation occurs when the channel is thinner than 3.0 nm due to strong quantum confinement induced large potential variations over the channel. We show that the device channel width must be at least 0.3 mu m to avoid percolative "pinch off" for 0.5 mu m channel length devices. Theoretical analysis performed on the devices agrees well with the experimental data and provides important guidelines to model and optimize the devices for circuit design. (C) 2008 American Institute of Physics.