Abstract
Chaos has been used in cryptography for years and many chaotic cryptographic systems have been proposed. Their securities are often evaluated by conducting conventional statistical tests, however few studies have referred to the security issue of the chaotic hardware cryptographic systems. This paper evaluates the security of the chaotic cryptographic system from a hardware perspective by using the side channel analysis attack. First, a chaotic block cryptosystem is designed and implemented based on an Atmel microcontroller. Then the conventional statistical security tests, including SP 800-22 test, characters frequency test, avalanche test etc., are used to verify its security performance. In the meantime, the correlation power analysis attack is carried out for the security evaluation. Experimental results demonstrate that even though the chaotic cryptographic system can pass the conventional statistical tests, it still has the probability to be attacked from a hardware perspective using the leaked side channel information including execution time and power consumption etc. This paper proposes another way to analyze the security of the chaotic cryptosystem, which can aid designing mechanisms to enhance the security of the hardware cryptosystems in the future.