Abstract
Being focused on the derivation and VLSI implementation of low-complexity multicarrier demultiplexers (DEMUXs) for on-board processing (OBP) satellites, three major contributions are presented in this thesis: 1. A systematic approach based on the multirate signal flow graph (MSFG) representation and transforms to multirate system optimization is proposed. A major advantage of this approach is that it provides clearer structural information and avoids tedious and ad hoc mathematical manipulations in multirate network simplification. Many computationally efficient multicarrier DEMUX structures can be derived using the MSFG approach. A number of identities and transforms of MSFG are identified and summarized. 2. A simple multirate VLSI modeling method for efficient mapping from a computational structure to VLSI architecture is also proposed. With this method, the efficiency of complexity, power consumption, and throughput of a VLSI architecture can be considered jointly and trade-offs between them can be made by imposing different constraints. For given system parameters and a DEMUX structure, the searching for an optimal VLSI architecture becomes the determination of the configuration for basic components. The proposed method provides technology-independent estimation for VLSI complexity and power consumption. Examples illustrate the usefulness of the proposed method for comparative study of alternative VLSI architectures. 3. A low-complexity binary tree architecture, known as the TM2-tree, is proposed for efficient VLSI implementation. In a TM2-tree, not only the inner product (IP) is time-shared amongst stage channels, but the IP itself is also realized by time-sharing a common complex arithmetic processor for both the lowpass and the highpass filtering processes at a lower hierarchy level. A gate array ASIC design for an 8-channel tree DEMUX based on the TM2-tree architecture is also presented. Additionally, issues on bandpass sampling, FDM signal channel stacking, efficient complex filter structures, flexible DEMUX structures, bit-serial arithmetic and techniques, systolic DFT and FIR architectures, etc. are also discussed and some novel structures and interesting results are provided in the relevant chapters.