Abstract
Economical operation of future satellite systems for mobile communications can only be fulfilled by using dedicated on-board processing satellites, which would allow both cheap earth terminals and lower space segment costs. With on-board modems and codecs, the up-link and down-link can be optimized separately. An attractive scheme is to use FDMA/SCPC on the up-link and TDM on the down-link. This scheme allows mobile terminals to transmit a narrow band, low power signal, resulting in smaller dishes and HP As with lower output power. On the up-link, there are hundreds to thousands of FDM channels to be demodulated on-board. The most promising approach is the use of all-digital multicarrier demodulators (MCDs), where analogue and digital hardware are efficiently shared amongst channels, and digital signal processing is used at an early stage to take advantage of VLSI implementation. A MCD consists of a channelliser for separation of FDM channels, followed by individual modulators for each channel. Major research areas in MCDs are in multirate digital signal processing, and the optimal estimation for synchronization, which form the basis of the thesis. Complex signal theories are central to the development of structured approaches for the sampling and processing of bandpass signals, which are the foundations in both channelliser and demodulator design. In multirate DSP, novel polyphase theories replace many ad-hoc, tedious and error-prone design procedures. For example, a polyphase-matrix-DFT channelliser includes all efficient filter bank techniques as special cases. Also, a polyphase-lattice filter is derived, not only for sampling rate conversion, but also capable of sampling phase variation, which is required for symbol timing adjustment in all-digital demodulators. In modulation schemes, a systematic survey is reported, based on two expressions that includes all formats in linear and constant envelope modulation. In synchronization techniques, classifications according to the criterion of statistical optimization, the data dependency, and the method of parameter extraction, reflect the inherent complexity and performance of numerous existing algorithms. The designs of two new algorithms are presented: a differential decision frequency error detector that is simple and fast; a dual-comb-filter frequency/timing error detector that is targeted at VLSI implementation. The real-time implementation of a complete 4x16 kb/s MCD for the T-SAT project is described in detail, which proved many of the structured design concepts developed in the thesis. The requirements of software tools for various levels of simulation in multirate DSP and communications are analysed. This led to the implementation of a data-flow oriented simulation system, which was used in all research work in the thesis.