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Dynamic Queuing for Approximate Fairness in Programmable Shared Memory Switches
Conference proceeding

Dynamic Queuing for Approximate Fairness in Programmable Shared Memory Switches

Minghui Chang, Yunqi Gao, Bing Hu, Pei Xiao, Shicong Zhang, Chenhui Gu and Yisha Liu
2025 IEEE 26th International Conference on High Performance Switching and Routing (HPSR 2025), pp.1-6
IEEE Workshop on High Performance Switching and Routing
26th IEEE International Conference on High Performance Switching and Routing (HPSR 2025) (Osaka, Japan, 20/05/2025–22/05/2025)
20/05/2025

Abstract

Channel allocation fair queueing Memory architecture Merging Monitoring Packet scheduling Real-time systems Routing Scheduling algorithms shared memory switches Simulation Switches Throughput
To ensure fair bandwidth allocation for diverse application flows from data centers, effective bandwidth management in switches is critical. Modern switches often adopt shared memory architectures to enhance efficiency. Fair queuing mechanisms can achieve fair bandwidth allocation in switches. However, the state-of-the-art fair queuing mechanisms in shared memory switches suffer from excessive packet drops, leading to suboptimal network utilization. In this paper, we propose Dynamic Fair Queuing (DFQ), a novel mechanism that leverages a limited number of priority queues to achieve both high network utilization and fair bandwidth allocation. DFQ is based on two key novel ideas. First, DFQ presents dynamic admission thresholds to manage packet enqueuing by monitoring the accumulated arrived packet bits and the remaining buffer of the queues in real time. Second, DFQ employs queue splitting and merging to maximize the utilization of the shared memory pool while guaranteeing fairness. Simulation results demonstrate that DFQ significantly improves throughput, fairness, and network utilization, while reducing flow completion time by up to 44.1%.
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