Abstract
The thickness spatial modulation method can realize high-performance source/drain unilateral-crystallized (SDUC) poly-Si thin-film transistors (TFTs). The resulted thick source/drain, un-doped thin-channel device structure is also very promising for ultra-scaled device design. With a calibrated simulation model, the performance and process sensitivity of sub-100-nm SDUC TFTs were predicted by numerical simulations. The results indicate the manufacturability of the devices and highlight guidelines of optimizing the devices for different requirements of low-power or high-performance applications.