Abstract
The XG-PON standard for Passive Optical Networks (PONs) has imposed requirements for high performance processing in the architectures of network equipment. Especially, the designs of the 10Gbps receiver terminals and the network units (ONTs and ONUs) can become quite demanding. The current paper focuses on the XG-PON ONT/ONU receiver and presents an FPGA design realizing the decoding functions of the XG-PON physical adaptation layer: The scrambling, the RS(248,216) decoding and the Hybrid Error Correction (HEC) architectures, which are designed to communicate through a 64-bit bus. This work describes the components’ features and validates the results by showing the design’s performance on a Xilinx Kintex 7 FPGA.