Abstract
On board image data compression is an important feature of satellite remote sensing payloads. Reconfigurable Intellectual Property (IP) cores can enable change of functionality or modifications. A new and efficient lossless image compression scheme for space applications is proposed. In this paper, we present a lossless image compression IP core designed using AccelDSP, which gives users high level of flexibility. One typical configuration is implemented and tested on an FPGA prototyping board. Finally, it is integrated successfully into a System-on-Chip platform for payload data processing and control.