Abstract
Tensor contractions are a core computational primitive in scientific computing, machine learning, and quantum simulation. Achieving high performance for these operations on modern hardware requires not only selecting efficient computation kernels but also carefully orchestrating tensor memory layouts to match hardware-friendly formats. However, existing approaches such as Transpose–Transpose–GEMM–Transpose (TTGT) and GEMM-like Tensor–Tensor multiplication (GETT) either incur high data movement costs or sacrifice peak compute utilization. We present a compiler-based framework for optimizing tensor contraction expressions by systematically managing data layout to maximize throughput. At its core is an intermediate representation (IR) that explicitly separates transposition from computation and explicitly encodes associated layout constraints, enabling a two-phase optimization strategy: first, full expansion of the IR to expose all layout transformation opportunities; second, selective permutation fusion based on profile-guided optimization(PGO) to balance memory movement and compute efficiency. The optimized IR is lowered to high-performance backends, using BLAS to leverage hardware-accelerated matrix operation where beneficial, and fused GETT for bandwidth-sensitive cases. Experimental results on 24 binary contraction benchmarks and 8 tensor network expressions demonstrate substantial runtime improvements over state-of-the-art libraries, 2.42× 2.42× speedup on CPU and 1.49× 1.49× on GPU for tensor network expression. These results highlight the critical role of layout orchestration in unlocking the full potential of modern hardware tensor computation.